1. Field
The present invention relates to a digital processor and, more particularly to a processor which receives integer data, converts it into logarithmic data, operates thereon, and reconverts it into integer data.
2. Description of the Prior Art
Systems for converting integer data into logarithmic data, operating on the logarithmic data, and then reconverting it into integers are well known. See IEEE Transactions On Computers, Vol. C-32, No. 6, June 1983, pages 531-534, wherein a logarithm arithmetic calculating unit is disclosed. In addition, see Eletron. Lett. 7:56-58 (1971), pages 215-217, article entitled "Digital Filtering Using Logarithmic Arithmetic"; IEEE Transactions On Computers, Vol. 24, No. 8, August 1975, pages 761-765, article entitled "Multiplication Using Logarithms Implemented With Read-Only Memory" by Brubaker, et al.; IEEE Transactions On Acoustics, Speech And Signal Processing, Vol. ASSP-31, No. 1, February 1983, pages 232-234; IEEE Transactions On Computers, December 1975, pages 1238-1242; IEEE Transactions On Computers, Vol. C-32, No. 6, June 1983, pages 526-530; see also "The Implementation Of Logarithmic Arithmetic" by Bechtolsheim, et al., Stanford University, March 7, 1981; and IEEE Transactions On Acoustics, Speech And Signal Processing, Vol. ASSP-28, No. 6, December 1980, article entitled "Error Analysis of Recursive Digital Filters Implemented With Logarithmic Number Systems" by Kurokawa, et al.
All of the prior art systems have converted integer numbers into logarithmic numbers, operated thereon, and reconverted the logarithmic numbers back into integers, based upon either software or hardware implementation.
In software implementation, the problem typically has been that it requires a number of machine cycles to accomplish the task. In certain applications, such as digital signal processing or Fourier analysis, speed is a requisite element. Thus, software conversion is impractical.
In the hardware implementation of a logarithmic calculating unit or logarithmic processor, the greatest impediment to implementation is the cost of the hardware. The look-up table to convert and operate on logarithms has generally required extensive amount of memory and, consequently, cost is the drawback.
Digital memory circuits, such as ROM's (Read-Only Memories) or RAM's (Random Access Memories), are well-known in the art. These memory circuits receive an input digital signal, which represents the location of the memory cell to which data is desired to be accessed. Typically, the input digital signal is called an address signal. In response to the address signal, the memory content at the location of the address is then either supplied to the memory circuit or is retrieved therefrom. These memory circuits are deterministic in that, for each address signal, there is a unique memory location from which the data associated with that memory location is either retrieved from the memory cell or is supplied to that particular memory cell.
Digital comparators are also well-known in the art. A digital comparator receives an input digital signal and compares it to a stored digital signal. In response to that comparison, an output signal is generated.
Finally, flash analog to digital converters are also well-known in the art. A flash A-D converter is a high speed analog-to-digital converter in which analog data is supplied to a linear array. A plurality of analog comparators in the array compares the analog signal and produces a plurality of digital signals. Each analog comparator is a reference voltage comparator, or is an A-D converter.